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fully accurate, 16 - bit, unbuffered v out , quad spi interface, 2.7 v to 5. 5 v nano dac in a tssop ad5066 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility i s assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.co m fax: 781.461.3113 ? 2009 C 2010 analog devices, inc. all rights reserved. features low p ower quad 16 - bit nano dac, 1 lsb inl low total unadjusted er ror of 0.1 mv typically low zero code error of 0.05 mv typically individual ly buffered reference pins 2.7 v to 5.5 v power supply specified over full code range of 0 to 65535 power - o n r eset to zero scale or mid scale p er channe l power - down with 3 p ower - d own f unctions hardware ldac with software ldac override function clr small 1 6 - lead tssop f unction to programmable code applicati ons process c ontrol data a cquisition s ystems portable b attery - p owered i nstruments digital g ain and o ffset a djustment programmable voltage and current sources general description the ad50 66 is a low power, 16 - bit quad - channel, unbuffered voltage out put nano dac ? offering relative accuracy specifica - tions of 1 lsb inl with individual reference pin s and can operate from a single 2.7 v to 5.5 v supply . the ad50 66 also offer s a differential accuracy specification of 1 lsb dnl . r eference buffer s are also provided on - chip. the part use s a versatile 3 - wire , low power schmitt trigger serial interface that operates at clock rates up to 5 0 mhz and is compatible with standard spi?, qspi?, microwire?, a nd most dsp interface standards . the ad50 66 incorporates a power - on r eset circuit that ensures the dac output powers up to zero scale or midscale and remains there until a valid write to the device takes place . total unadjusted error for the part is <0.8 mv. zero code error for the part is 0.05 mv typically. the ad5066 co ntai n s a power - down feature that reduces the current consumptio n of the device to typically 400 na at 5 v and provide s software selectable output loads while in power - down mode. the outputs of all dacs can be updated simultaneously using the hardware ldac function, with the add ed functionality of user soft ware select able dac channels to update simultan eously. there is also an asynchronous clr that clears all dac s to a software - selectable code 0 v, midscale, or full scale . product highlights 1. quad channel available in 16 - lead tssop, 1 lsb inl. 2. individual ly buffered voltage reference pins . 3. tue = 0.8 mv max and z ero code e rror = 0.1 mv max. 4. high speed serial interface with clock speeds up to 5 0 mhz. 5. three power - down modes available to the user. 6. reset t o known output voltage ( zer o scale or midscale ). table 1 . related devices part no. description ad5666 q uad,16 - bit buffered d a c ,16 lsb inl, tssop ad5025 / ad5045 / ad5065 1 dual , 12 - /14 - / 16 - bit buffered nano da c, tssop ad5024 / ad5044 / ad5064 1 quad 16- bit nano dac , tssop ad5062 1 single, 16 - bit nano dac , sot - 23 ad5063 1 single, 16 - bit nano dac , msop ad5061 s ingle, 16 - bit nano dac, 4 lsb inl, sot - 23 ad50 40 / ad5060 1 14 - /1 6 - bit nano dac , sot - 23 1 1 lsb inl functional block dia gram interface logic input register din ldac gnd v dd ldac v ref a sync sclk ad5066 clr v out a v out b v out c v out d dac register dac a input register dac register dac b input register dac register dac c dac d input register dac register v ref b v ref c v ref d por power-down logic power-on reset 06845-001 figure 1.
ad5066 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical p erformance characteristics ............................................. 8 terminology .................................................................................... 14 theory of operation ...................................................................... 15 digital - to - analog converter .................................................... 15 dac architecture ....................................................................... 15 reference buffer ......................................................................... 15 serial interface ............................................................................ 15 input shift register .................................................................... 15 power - on reset .......................................................................... 17 clear code register ................................................................... 18 ldac function ........................................................................... 18 power supply bypassing and grounding ................................ 19 microprocessor interfacing ....................................................... 19 applications information .............................................................. 21 using a reference as a power supply ....................................... 21 bipolar operation ....................................................................... 21 using the ad5066 with a galvanically isolated interface .... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 8 /10 rev. 0 to rev. a change to minimum sync 7 /0 9 rev ision 0: initial version high t ime , single channel update parameter, table 4 ............................................... 5
ad5066 rev. a | page 3 of 24 specifications v dd = 2.7 v to 5.5 v , 2.0 v v ref a, v ref b, v ref c, v ref d v dd ? 0.4 v , a ll specifications t min to t max , unless otherwise noted. table 2 . parameter a grade 1 b grade 1 un it conditions/comments min typ max min typ max static performance 2 resolution 16 16 bits relative accuracy (inl) 0.5 4 0.5 1 lsb t a = ? 40c to +10 5c 0.5 4 0.5 2 t a = ? 40c to +125c differential nonlinearity (dnl) 0. 2 1 0. 2 1 lsb total unadjusted error (tue) 0. 1 0.8 0. 1 0.8 mv v dd = 2.7 v, v ref = 2 v zero - code error 0.05 0.1 0.05 0.1 mv all 0s loaded to the dac register zero - code e rror drift 3 0.5 0.5 v/c full - scale error 0.01 0.05 0.01 0.05 % fsr all 1s loaded to the dac register gain error 0.005 0.05 0.005 0.05 % fsr gain error drift 3 0.5 0.5 ppm p pm o f fsr/c dc crosstalk 3 1 5 1 5 v due to single - channel full - scale output change 5 25 5 25 v due to powering down (per channel) output characteristics 3 output voltage range 0 v ref 0 v ref v dc output impedance (normal mod e) 8 8 k? output impedance tolerance 10% dc output impedance dac in power -d own mode output connecte d to 100 k ? network 100 100 k ? o utput impedance tolerance 20 k ? output connected to 1 k ? network 1 1 k ? o utput impedance tolerance 400 ? powe r- up time 4 2.9 2.9 s dc psrr ? 120 ? 120 db v dd 10%, dac = full scale reference inputs reference input range 2 v dd ? 0.4 2 v dd ? 0.4 v reference current 0.002 1 0.002 1 a per dac channel reference input impedance 40 40 m? per dac channel logic inputs 3 input current 5 1 1 a input low voltage, v inl 0.8 0.8 v input high voltage, v inh 2 .2 2 .2 v pin capacitance 4 4 pf power requirements v dd 2.7 5.5 2.7 5.5 v all digital inputs at 0 v or v dd dac active, excludes load current i dd v ih = v dd and v il = gnd normal mode 6 2.5 3 2.5 3 ma all power - down modes 7 0.4 0.4 a 1 temperature range is ?40 c to +125c, typical at 25c. 2 linearity calculated using a code range of 0 to 65,535; output unloaded. 3 guaranteed by design and characterization; not production tested. 4 time taken to exit power - down mode and enter nor mal mode, 32 nd clock edge to 90% of dac mid scale value, output unloaded . 5 current flowing into individual digital pins. v dd = 5.5 v; v ref = 4.096 v; code = midscale. 6 interface inactive. all dacs active. dac outputs unloaded . 7 all four dacs powered down .
ad5066 rev. a | page 4 of 24 ac characteristics v dd = 2.7 v to 5.5 v, 2.0 v v ref a, v ref b, v ref c, v ref d v dd ? 0.4 v a ll specifications t min to t max , unless otherwise noted. table 3 . parameter 1 , 2 min typ max unit conditions/comments 3 dynamic performace output voltage settling time 7. 5 10 s ? to ? scale settling to 2 lsb , single channel update, output unloaded output voltage settling time 1 2 15 s ? to ? scale settling to 2 lsb, all channel update, output u n loaded slew rate 1.7 v/s digital -to - analog glitch impulse 3 nv -s ec 1 ls b change around major carry reference feedthrough ?70 db v ref = 3 v 0.5 v p - p, frequency = 6 0 hz to 20 mhz digital feedthrough 0.02 nv -s ec digital crosstalk 1.7 nv -s ec analog crosstalk 3.7 nv -s ec dac -to - dac crosstalk 5. 4 nv -s ec total harmonic distortion ?83 db v ref = 3 v 0.2 v p -p, frequency = 10 khz output noise spectral density 30 nv/ hz dac code = 0x80 00, 1 khz 25 nv/ hz dac code = 0x80 00, 1 0 khz output noise 4.7 v p -p 0.1 hz to 10 hz 1 temperature range is ?40 c to + 125c, typical a t +25c. 2 see the terminology section. 3 guaranteed by design and characterization; not production tested.
ad5066 rev. a | page 5 of 24 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10 % to 90% of v dd ) and timed from a voltage level of (v il + v ih )/ 2, v dd = 2.7 v to 5.5 v, a ll specifications t min to t max , unless otherwise noted. see figure 2 . table 4 . parameter 1 symbol min typ max unit sc lk cycle time t 1 20 ns sclk high time t 2 10 ns sclk low time t 3 10 ns sync to sclk falling edge set - up time t 4 17 ns data set - up time t 5 5 ns data hold time t 6 5 ns sclk falling edg e to sync rising edge t 7 5 30 ns minimum sync high time t 8 single channel update 3 s all channel update 8 s sync rising edge to sclk fall ignore t 9 17 ns l dac pulse width low t 10 20 ns sclk falling edge to ldac rising edge t 11 20 ns clr pulse width low t 12 10 ns sclk falling edge to ldac falling edge t 13 10 ns clr pulse activation time t 14 10.6 s 1 maximum sclk frequency is 50 mhz. guaranteed by design and characterization; not production tested. t 4 t 3 s c l k sy n c d i n t 1 t 2 t 5 t 6 t 7 t 8 db 3 1 t 9 t 1 0 t 1 1 l da c 1 l da c 2 t 1 3 1 a sy nchr o n o u s l dac u p da t e m o d e . 2 sy nchr o n o u s l dac u p da t e m o d e . c l r t 1 2 t 1 4 v o u t db 0 06845-003 figure 2 . serial write operation
ad5066 rev. a | page 6 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5 . parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out x to gnd ?0.3 v to v dd + 0.3 v v ref x to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +125c storage temperature range ?65c to +150c junction temperature (t j max ) +150c tssop package power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature snpb 240c pb - free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to th e device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended p eriods may affect device reliability. esd caution
ad5066 rev. a | page 7 of 24 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 v dd v ref b v out c v out a v ref a por 16 15 14 13 12 1 1 10 9 din gnd v out b v ref c v ref d v out d sclk ad5066 t op view (not to scale) ldac sync clr 06845-004 figure 3. pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 ldac load dac. logic input . this is used to update the dac register and , consequently , the analog outputs. when tied permanently low, the addressed dac register is updated on the falling edge of the 32 nd clock. if ldac is held high during the write cycle, the addressed dac input shift register is updated but the output is held off until the falling edge of ldac . in this mode, all analog outputs can be updated simultaneously on the falling ed ge of ldac . 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the shift regis ter. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32 nd falling edge, the rising edge of sync acts as an interrupt , and the write sequence is ignored by the device. 3 v dd power supply input. the ad5066 can be operated from 2.7 v to 5.5 v. decouple the supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd . 4 v ref b external reference voltage input for dac b . 5 v ref a external reference vol tage input for dac a. 6 v out a unbuffered analog output voltage from dac a. 7 v out c unbuffered analog output voltage from dac c. 8 por power - on reset pin. tying this pin to gnd powers the dac outputs to zero scale on power -up . tying this pin to v dd pow ers the dac outputs to midscale. 9 v ref c external reference voltage input for dac c . 10 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code register zero, midscale, or full scale. default setting clears the output to 0 v. 11 v ref d external reference voltage input for dac d. 12 v out d unbuffered analog output voltage from dac d. 13 v out b unbuffered analog output voltage from dac b. 14 gnd ground reference point for all circuitry on the part. 15 din serial data input. t his device has a 32 - bit shift register. data is clocked into the register on the falling edge of the serial clock input. 16 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be t ransferred at rates of up to 50 mhz.
ad5066 rev. a | page 8 of 24 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 10,000 20,000 30,000 40,000 50,000 60,000 inl error (lsb) code v dd = 5v v ref = 4.096v t a = 25c 06845-105 figure 4. inl error vs. code ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 10,000 20,000 30,000 40,000 50,000 60,000 dnl error (lsb) code v dd = 5v v ref = 4.096v t a = 25c 06845-106 figure 5. d nl error vs. code ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0 10,000 20,000 30,000 40,000 50,000 60,000 total unadjusted error (mv) code v dd = 5v v ref = 4.096v t a = 25c 06845-107 figure 6. total unadjusted error vs. code ?0.5 ?0.4 ?0.3 ?0.2 0 0.1 ?0.1 0.2 0.3 0.4 0.5 2 3 4 5 inl (lsb) refer e nce v ol t age ( v ) m in i n l m ax i n l v dd = 5v t a = 25c 06845-108 figure 7. inl vs. reference input voltage ?0.5 ?0.4 ?0.3 ?0.2 0 0.1 ?0.1 0.2 0.3 0.4 0.5 2 3 4 5 dnl (lsb) refer e nce v ol t age ( v ) m in d n l m ax d n l v dd = 5.5v t a = 25c 06845-109 figure 8. dnl vs. reference input voltage ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 2 3 4 5 total unadjusted error ( v) reference voltage (v) max tue min tue v dd = 5.5v t a = 25c 06845-110 figure 9. total unadjusted error vs. reference input voltage
ad5066 rev. a | page 9 of 24 gain error (% f s r) refe r enc e v o lt age ( v ) ?0. 0 10 ?0.0 0 5 0 0.00 5 0. 0 10 2 3 4 5 v dd = 5.5v t a = 25c 06845-111 figure 10 . gain error vs. reference input voltage 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 2 3 4 5 zero-scale error (mv) reference voltage (v) v dd = 5.5v t a = 25c 06845-112 figure 11 . zero - code er ror vs. reference input voltage ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 ?40 ?20 0 20 40 60 80 100 120 inl (lsb) temperature (c) max inl min inl v dd = 5v v ref = 4.096v 06845-113 figure 12 . inl vs. temperature ?1.2 ?0.8 ?1.0 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 ?40 ?20 0 20 40 60 80 100 120 dnl (lsb) temperature (c) max dnl min dnl v dd = 5v v ref = 4.096v 06845-114 figure 13 . d nl vs. temperature ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (v) temperature (c) max tue min tue v dd = 5v v ref = 4.096v 06845-115 figure 14 . total unadjusted error vs. temperature ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?40 ?20 0 20 40 60 80 100 120 zero-scale error (v) temperature (c) v dd = 5v v ref = 4.096v 06845-116 figure 15 . zero - code erro r vs. temperature
ad5066 rev. a | page 10 of 24 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0.0005 0 0.0010 0.0015 0.0020 ?40 ?20 0 20 40 60 80 100 120 gain error (%fsr) temperature (c) v dd = 5v v ref = 4.096v 06845-117 figure 16 . gain error vs. temperature ?0. 0 10 ?0.0 0 5 0 0.00 5 0. 0 10 2. 7 3.2 3.7 4.2 4.7 5.2 e rr or ( % fsr) v dd (v) fu l l-s c ale e rr or gain e rr or v dd = 5v v ref = 4.096v t a = 25c 06845-118 figure 17 . gain e rror and f ull - s cale error vs. supply voltage 0 5 10 15 20 2.7 3.7 4.7 zero-scale error (v) v dd (v) v dd = 5v v ref = 4.096v t a = 25c 06845-119 figure 18 . zer o- code error vs. supply voltage 7 2.45 hits i dd power-up (ma) 6 5 4 3 2 1 0 2.50 2.55 2.60 2.65 2.70 v dd = 5v dac output unloaded t a = 25c 06845-120 figure 19 . i dd histogram v dd = 5.5 v 06845-139 60 50 40 30 20 10 0 0.2 0.4 0.6 i dd powerdown ( a) hits 0.8 1.0 +12 5 c i dd powerdown +2 5 c i dd powerdown ?4 0 c i dd powerdown v dd = 5v t a = 25c dac output unloaded figure 20 . i dd power - down histogram 0 1 2 3 4 5 0 10,000 20,000 30,000 40,000 dac code i dd (ma) 50,000 60,000 06845-121 v dd = 5.5v v ref = 4.096v t a = 25c figure 21 . i dd vs. code
ad5066 rev. a | page 11 of 24 0 1 2 3 4 5 ?40 ?20 0 20 40 temperature (c) 60 80 100 120 i dd (ma) 06845-122 v dd = 5.5v v ref = 4.096v t a = 25c code = midscale figure 22 . i dd vs. temperature 2.7 3.0 3.5 4.0 4.5 supply voltage (v) 5.0 5.5 0 1 2 3 4 5 i dd (ma) 06845-123 v ref = 4.096v t a = 25c code = midscale figure 23 . i dd vs. supply voltage digital input voltage (v) i dd (ma) 0 2 4 6 8 10 0 1 2 3 4 5 6 06845-124 v dd = 5.5v v ref = 4.096v t a = 25c figure 24 . i dd vs . digital input voltage 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1 2 3 4 5 6 7 8 9 10 output voltage (v) time (s) 1/4 to 3/4 3/4 to 1/4 06845-125 v dd = 4.5v v ref = 4.096v output amplifier = ad797 t a = 25c dac load = 9pf figure 25 . settling time ch1 2.00v ch3 2.00v ch2 2.00v m10.00ms a ch1 640mv t 30.20% v dd v ref v out 06845-126 v ref = 4.096v t a = 2 5 c figure 26 . por to 0 v ch1 2.00v ch3 2.00v ch2 2.00v m10.00ms a ch1 640mv t 30.20% v dd v ref v out 06845-127 v dd = 5.5v v ref = 4.096v figure 27 . por to ms
ad5066 rev. a | page 12 of 24 ch1 5v ch2 500mv m2s a ch2 1.2v 2 1 t 55% ch1 = sclk ch2 = v out v dd = 5v power-up to midscale output unloaded 06845-128 figure 28 . exiting pd to ms ?15 ?10 ?5 0 5 10 15 ?2 0 2 4 6 8 10 time (s) glitch amplitude (mv) v dd = 5v v ref = 4.096v t a = 25c code = 0x8000 to 0x7fff output unloaded with 5k ? and 200pf 06845-129 figure 29 . glitch ?15 ?10 ?5 0 5 10 15 ?2 0 2 4 6 8 10 time (s) glitch amplitude (mv) v dd = 5v v ref = 4.096v t a = 25c 06845-130 figure 30 . analog crosstalk ?15 ?10 ?5 0 5 10 15 ?2 0 2 4 6 8 10 time (s) glitch amplitude (mv) v dd = 5v v ref = 4.096v t a = 25c 06845-131 figure 31 . digital crosstalk ?20 ?15 ?10 ?5 0 5 10 20 15 ?2 0 2 4 6 8 10 time (s) glitch amplitude (mv) v dd = 5v v ref = 4.096v t a = 25c 06845-132 figure 32 . dac - to- dac crosstalk 4 3 2 1 0 ?1 ?2 ?3 ?4 0 1 4 7 output voltage (v) time (seconds) 2 5 8 3 6 9 10 06845-133 v dd = 5v v ref = 4.096v t a = 25c figure 33 . 1/ f noise
ad5066 rev. a | page 13 of 24 0 ?20 ?50 ?80 ?100 5 10 30 40 55 06845-016 v out level (db) frequency (khz) ?90 ?70 ?60 ?10 ?30 ?40 20 50 v dd = 5v, t a = 25oc dac loaded with midscale v ref = 3.0v 200mv p-p figure 34 . t otal h armonic d istortion ch1 5.00v ch2 2.00v m2.00ms a ch1 1.80v t 10.20% clr v out 06845-135 figure 35 . hardware clr 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 output voltage (v) time (s) 3/4 to 1/4 1/4 to 3/4 06845-136 v dd = 4.5v v ref = 4.096v t a = 25c figure 36 . slew rate ch1 50.0mv ch2 5.00v m4.00s a ch2 1.80v t 9.800% last sclk v out ch1 peak to peak 155mv 06845-137 v dd = 5v v ref = 4.096v t a = 2 5 c figure 37 . glitch upon entering power down ch1 50.0mv ch2 5.00v m4.00s a ch2 1.80v t 9.800% last sclk v out ch1 peak to peak 159mv 06845-138 v dd = 5v v ref = 4.096v t a = 2 5 c figure 38 . glitch upon exiting power down
ad5066 rev. a | page 14 of 24 terminology relative accuracy or integral nonlinearity (inl) r elative accuracy or inl is a measure of the maximum deviation in lsbs from a straight line passing th rough the endpoints of the dac transfer function. figure 4 , figure 5 , and figure 6 show typical inl vs. code plots . differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures mono - tonicity. figure 7 , figure 8 , and figure 9 show typical dnl vs. code plots . zero - code error zero - code error is a measure of the output error when zero code (0x0000) is loaded into the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5066 , because the outp ut of the dac cannot go below 0 v . zero - code error is expressed in millivolts. figure 17 shows a typical zero - code error vs. s upply voltage plot . gain error gain error is a measure of the span error of the dac . it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full - scale range. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed i n (p pm of full - scale range)/c. zero - code error drift zero - code error drift is a measure of the change in zero - code error with a change in temperature. it is expressed in microvolts per degrees celsius . full - scale error full - scale error is a measure of the out put error when a full - scale code (0xffff) is loaded into the dac register. ideally, the output should be v ref ? 1 lsb. full - scale error is expressed as a percentage of the full - scale range. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes sta te. it is normally specified as the area of the glitch in n a novolts per second and is measured when the digital input code is changed by 1 lsb at the major c arry tra nsition (0x7fff to 0x8000). see figure 28. dc power supply rejection ratio (psrr) dc psrr indicates how the output of the dac is affected by changes in the supply voltage. dc psrr is the ratio of the change in v out to a ch ange in v dd for full - scale output of the dac . it is measured in decibels. dc crosstalk dc crosstalk is the dc change in the output level of one dac in respo nse to a change in the output of another dac. it is meas ured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in microvolts. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the d ac output is not being updated (that is, ldac digital feedthrough is high). it is expressed in decibels. digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device bu t is measured when the dac is not being written to ( sync digital crosstalk held high). it is specified in nanovolts per second and measured with one sim ultaneous din and sclk pulse loaded to the dac . digital crosstalk is the glitch impul se transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nanovolts per second . analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s or vice versa) while keeping ldac high and then pulsing dac -to - dac crosstalk ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nanovolts per second . dac - to - dac crosstalk is the glit ch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full - scale code change (all 0s to al l 1s or vice versa) with ldac total harmonic distortion (thd) low and monitoring the output of another dac. the energy of the glitch is expressed in nanovolts per second . thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5066 rev. a | page 15 of 24 theory of operation digital-to-analog converter the ad5066 is a quad 16-bit, serial input, voltage output nano dac. the part operates from supply voltages of 2.7 v to 5.5 v. data is written to the ad5066 in a 32-bit word format via a 3-wire serial interface. the ad5066 incorporates a power-on reset circuit to ensure the dac output powers up to a known output state. the devices also have a software power-down mode that reduces the typical current consumption to typically 400 na. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? ?? n refin out d vv 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register (0 to 65,535). n is the dac resolution. dac architecture the dac architecture of the ad5066 consists of two matched dac sections. a simplified circuit diagram is shown in figure 39. the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either gnd or the v ref buffer output. the remaining 12 bits of the data word drive the s0 to s11 switches of a 12-bit voltage mode r-2r ladder network. 2r s0 v ref 2r s1 2r s11 2r e1 2r e2 2r e15 2r v out 12-bit r-2r ladder four msbs decoded into 15 equal segments 06845-005 figure 39. dac ladder structure reference buffer the ad5066 operates with an external reference. each of the four on-board dacs has a dedicated voltage reference pin that is buffered. the reference input pin has an input range of 2 v to v dd ? 0.4 v. this input voltage is then used to provide a buffered reference for the dac core. serial interface the ad5066 has a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, microwire, and most dsp interface standards. see figure 2 for a timing diagram of a typical write sequence. input shift register the input shift register is 32 bits wide (see figure 40). the first four bits are dont cares. the next four bits are the command bits, c3 to c0 (see table 7), followed by the 4-bit dac address bits, a3 to a0 (see table 8), and finally the bit data-word. the data-word comprises of a 16-bit input code followed by four dont care bits (see figure 40). these data bits are transferred to the input register on the 32 nd falling edge of sclk. commands can be executed on individually selected dac channels or on all dacs. table 7. command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 transfer contents of input register n to dac register n 0 0 1 0 write to input register n and update all dac registers 0 0 1 1 write to input register n and update dac register n 0 1 0 0 power down/power up dac 0 1 0 1 load clear code register 0 1 1 0 load ldac register 0 1 1 1 reset (power-on reset) 1 0 0 0 reserved 1 0 0 1 reserved 1 1 1 1 reserved table 8. dac input register address bits address (n) selected dac channel a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x x x x xxx db31 (msb) db0 (lsb) data bits 06845-007 figure 40. input shift register content
ad5066 rev. a | page 16 of 24 the write sequence begins by bringing the sync line low. bringing the sync line low enables the din and sclk input buffers. data fr om the din line is clocked into the 32 - bit shift register on the falling edge o f sclk. the serial clock frequency can be as high as 50 mhz, making the ad5066 compatible with high speed dsps. on the 32 nd falling clock edge, the last data bit is clocked in , and the programmed function is executed, that is, a change in the i nput registe r co ntents (see tabl e 8 ) and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be br ought high for a minimum of 2 s ( single - chann el update , see the t 8 parameter in table 4 ) before the next write sequence so that a falling edge of sync can initiate the next write sequence. idle sync high between write sequences for even lower power operation of the part. sync interrupt in a normal write sequence, the sync line is kept low for at least 32 falling edges of sclk, and the dac is updated on the 32 nd falling edge. however, if sync is brought high before the 32 nd falling edge, this acts as an interrupt to the write sequence. the input shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs ( see figure 42). power - down modes the ad5066 can be configured through software, in one of four different modes : normal mode (default) and three separate power - down modes (see table 9 ). any or all dacs can be powered down . command 0100 is reserved for the power - down function (see table 7 ). these power - down modes are software - programmable by setting two bi ts, bit db9 and bit db8, in the inpu t shift register . table 9 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac a to dac d) can be powered down to the selected mode by setting the cor res ponding four bits (d b3, db2, db1, db0) to 1. see table 10 for the contents of the input shift register during power - down/power - up operation . when bit db9 and bit db8 in the control reg ister are set to 0, the part is configured in normal mode with its normal power consumption of 2.5 ma at 5 v. however, for the three power - down modes, the supply current falls to 0.4 a if all the chann els are powered down . not only does the supply current fall, but the output pin i s also internally switched from the output of the dac t o a resistor network of known values. this has the advant age that the output impedance of the part is known while the part is in power - down mode. there are three different options : t he output is connected internally to gnd through eith er a 1 k ? or a 100 k ? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 41. resis t or network v out dac power-down circuit r y 06845-008 figure 41 . output stage during power - down mode the bias generator, dac core , a nd other associated linear circuitry are shut down when all channels are powered down . how ever, the contents of the dac register are unaffected when in power - dow n mode . the time to exit power - down mode is typica lly 2.9 s (see fig ure 27) . table 9 . modes of operation db9 db8 operating mode 0 0 normal operation power - down modes 0 1 1 k ? to gnd 1 0 100 k ? to gnd 1 1 three - state sclk din db31 db0 invalid write sequence: sync high before 32 nd falling edge valid write sequence: output updates on the 32 nd falling edge db31 db0 sync 06845-017 figure 42 . sync interrupt facility
ad5066 rev. a | page 17 of 24 power - on reset the ad5066 contains a power - on reset circuit that controls the output voltage during power - up. b y connecting the por pin low, the ad5066 output powers up to 0 v; by connecting th e por pin high, the ad5066 output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in appl ications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power - on reset code. command 0111 is reserved for this reset function (see table 7 ). any events on ldac or clr during power - on reset are ignored. table 10 . 32- bit input shift register contents for power - up/power - down function msb lsb db31 to db28 db27 db26 db25 db24 db23 to db20 db10 to db19 db9 db8 db4 to db7 db3 db2 db1 db0 x 0 1 0 0 x x pd1 pd0 x dac d dac c dac b dac a dont care s command bits (c2 to c0) add ress bits (a3 to a0) dont care s dont care s power - down mode do nt care s power - down/power - up channel selection set bit to 1 to select
ad5066 rev. a | page 18 of 24 clear code register the ad5066 has a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringi ng the clr line low clears the conte nts of the input register and the dac registers to the data contained in the user - configurable clr register and sets the analog outputs accordingly (see table 11) . this function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. these clear code values are user - programmable by setting two bits, bit db1 and bit db0, in the control register (see table 11 ). the default setting clears the outputs to 0 v. command 0101 is reserved for loading the clear code register (see table 7 ). table 11 . clear code register db1 ( cr1 ) db0 ( cr0 ) clears to c ode 0 0 0x0000 0 1 0x8000 1 0 0xffff 1 1 no operation the part exits clear code mode on the 32 nd falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. the clr pulse activation time ( the falling edge of clr to when the output starts to change ) is typically 10.6 s . see table 13 for contents of the input shift register during the loading clear code register operation . ldac function hardware ldac pin the outputs of all dacs can be updated simultaneously using the hardware ldac pin, as shown in figure 2 . there are two methods of using the hardware ldac pin : syn chronously ( ldac permanently low) and asynchronously ( ldac pulsed) . synchronous ldac : ldac is held permanently low. after new data is read, the dac registers are updated on the fallin g edge of the 32 nd sclk pulse, provided ldac is held low. asynchronous ldac : ldac is held high then pulsed low to update. the outputs are not updated at the same time tha t the input re gisters are writt en to. when ldac is pulsed low, the dac registers are updated with the contents of the input registers. command 0001, 0010 and 0011 (see table 7 ) update the dac register/registers , regardless of the level of the ldac pin software ldac function writing to the dac using command 0110 loads the 4 - bit ldac register (db3 to db0). the default for each channel is 0; that is, the ldac pin works normal ly. setting the bits to 1 updates the dac channel regardless of the state of the hardware ldac pin, so that it ef fectively sees the hardware ldac pin as being tied low (see table 12 for the lda c register mode of operation.) this flexibility is useful in applications where the user wants to simultaneously update select channels while the remainder of the channels are synchronously updating. table 12. load l dac ldac bits (db3 to db0) register ldac pin ldac operation 0 1/0 determined by ldac pin 1 x 1 dac channels update, overrides the ldac pin; dac channels see ldac as 0 1 x = dont care. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 14 ). setting the ldac bits (db0 to db3) to 0 for a dac channel means that this channels update is controlled by the hardware ldac pin. table 13 . 32- bit inpu t shift register contents for clear code function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db2 to db19 db1 db0 x 0 1 0 1 x x x x x 1/0 1/0 dont care s c ommand bits (c3 to c0) address bits (a3 to a0) dont care s clear code register (cr1 to cr0) table 14. 3 2 - bit input shi ft register contents for ldac msb overwrite function lsb db31 to db28 db27 db26 db2 5 db24 db23 to db20 db4 to db19 db3 db2 db1 db0 x 0 1 1 0 x x dac d dac c dac b dac a dont care s command bits (c3 to c0) add re ss bits (a3 to a0) dont care s dont care s se tting ldac bit to 1 override ldac pin
ad5066 rev. a | page 19 of 24 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5066 should have separate analog and digital sec tions. if the ad5066 is in a system where other devices require an agnd - to - dgnd con - nection, make the connection at one point only and as close as possible to the ad5066. bypass t he power supply to the ad5066 with 10 f and 0.1 f capacitors. the capacitor s should be physically as close as possible to the device, with the 0.1 f capacitor , ideally , right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resis tance and l ow effective series inductance , typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should hav e as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. shield the c locks and other fast switching digital signals from other parts of the board by digital ground. avoid crossover of digital and analog s ignals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only , and the signal traces are placed on the solder side. however, this is not always possible with a 2 - layer board. microprocessor inter facing ad5066 to black fin ? adsp - bf53x interface figure 43 shows a serial interface between the ad5066 and the blackfin adsp - bf53 x microprocessor. the adsp - bf53 x processor family incorporates two dual - channel synchronous serial por ts, sport1 and sport0, for serial and multipro - cessor communications. using sport0 to connect to the ad5066, the setup for the interface is as follows: dt0pri drives the din pin of the ad5066, tscl k0 drives the sclk of the parts , and tfs0 drives sync . ad5066* adsp-bf53x* sync tfs0 din dt0pri sclk tsclk0 *additional pins omitted for clarity. 06845-009 figure 43 . ad5066 to blackfin adsp - bf53x interface ad5066 to 68hc11/68l11 interface figure 44 shows a serial interface between the ad5066 and the 68hc11/68l11 microcontroller. sck o f the 68hc11/68l11 drives the sclk of the ad5066, and the mosi output drives din of the dac . a port line (pc7) drives the sync signal. ad5066* 68hc11/68l11* sync pc7 sclk sck din mosi *additional pins omitted for clarity. 06845-010 figure 44 . ad5066 to 68hc11/68l11 interface the setup conditions for c orrect operation of this interface are as follows: the 68hc11/68l11 is configured with its cpol bit as 0, and the cpha bit as 1. when data is being transmitted to the dac, the sync line is ta ken low (pc7). when the 68hc11/ 68l11 is c onfigured as described previously, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitt ed msb first. to load data to the ad5066, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure.
ad5066 rev. a | page 20 of 24 ad5066 to 80c51/80l51 interface figure 45 shows a serial interface between the ad5066 and the 80c51/80l51 microcontroller. the setup for the interface i s as follows: txd of the 80c51/ 80l51 drives sclk of the ad5066, rxd drives din on the ad5066, and a bit - programmable pin o n the port ( p3.3 ) drives the sync signal . when data is to be transmitted to the ad5066, p3.3 is taken low. the 80c51/80l51 transmit data in 8 - bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. to load d ata to the dac, p3.3 is left low after the first eight bits are transmitted, and a second , third , and fourth write cycle is initiated to transmit the second , third , and fourth byte of data. p3.3 is taken high following the completion of this cycle. the 80c 51/80l51 output the serial data in a format that has the lsb first. the ad5066 must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. ad5066* sync p3.3 sclk txd din rxd *additional pins omitted for clarity. 80c51/80l51* 06845-011 figure 45 . ad5066 to 80c512/80l51 interface ad5 066 to microwire interface figure 46 shows an interface between the ad5066 and any microwire - compatible device. serial data is clocked into the ad5066 on the fall ing edge of the sclk. ad5066* sync cs din sk sclk so *additional pins omitted for clarity. microwire* 06845-012 figure 46 . ad506 6 to microwire interface
ad5066 rev. a | page 21 of 24 applications information using a reference as a power supply because the supply current required by the ad5066 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (se e figure 47 ). this is espe - cially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for t he ad5066 . if the low dropout ref195 is used, it must supply 2.5 m a of current to the ad5066 with no load on the output of the dac. sync sclk din 15v 5v 4.5v v out x = 0v to 4.5v v dd v ref ref195 ad5066 3-wire serial interface ref194 06845-013 figure 47 . ref195 a s a power supply to the ad5066 bi polar operation the ad5066 has been designed for single - supply operation, but a bipolar output range is also possible using the circuit in figure 48. the circuit gives an output voltage range of 5 v. rail - to - rail operation at t he amplifier output is achieved using an ad8638 or ad8639 the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd dd o 536 , 65 wh ere : d = the input code in decimal (0 to 65,535). v dd = 5 v. r1 = r2 = 10 k ? . v 5 536 , 65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre - sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 3-wire serial interface r2 = 10k ? +5v ad820/ op295 +5.5v +5v ad5066 v dd v out r1 = 10k ? v ref 5v 0.1f 10f v ref ?5v 06845-014 figure 48 . bipolar operation with the ad5066 using the ad5066 wit h a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common - mode voltages that can occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. the ad5066 uses a 3 - wire serial logic interface, so the adum1300 three - channel digital isolator provides the required isolation (see figure 49 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad506 6. 0.1f gnd din sync sclk power 10f sdi sclk data ad5066 v out x v ob v oa v oc v dd v ic v ib v ia adum1300 5v regulator 06845-015 figure 49 . ad5066 with a galvanically isolated interface
ad5066 rev. a | page 22 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 50 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeter ordering guide mod el 1 temperature range package description package option power - on reset to code accuracy resolution ad5066bruz ?40c to +125c 16- lead tssop ru -16 zero 1 lsb inl 16 bits ad5066bruz - reel7 ?40c to +125c 16- lead tssop ru -16 zero 1 lsb inl 16 bits ad5 066aruz ?40c to +125c 16- lead tssop ru -16 zero 4 lsb inl 16 bits ad5066aruz - reel7 ?40c to +125c 16- lead tssop ru -16 zero 4 lsb inl 16 bits 1 z = rohs compliant part.
ad5066 rev. a | page 23 of 24 notes
ad5066 rev. a | page 24 of 24 notes ? 2009 C 2010 analog devices, inc. all rights res erved. trademarks and registered trademarks are the property of their respective owners. d06845 - 0 - 8/10(a)

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